The use of semiconductors as thermoelectric devices is well known in the art. Likewise, it is a common practice to arrange many P-type semiconductor thermal elements together with corresponding N-type thermal elements to form a side-by-side array and thus achieve an additive effect on the transfer of heat therethrough. U.S. Pat. No. 4,493,939, assigned to the assignee hereof, discloses such an array of thermal elements.
As noted in U.S. Pat. No. 4,493,939, one array of PN thermal elements may be stacked on top of another such array to effect an increased temperature gradient across the total stacked device. The stacking of PN thermal element arrays in a tiered manner poses a challenge insofar as electrical insulation must be maintained between the individual arrays, as well as a high degree of thermal conductivity to achieve an overall optimum transfer of heat.
The above-referenced patent discloses the use of a copper sheet epoxied between the tiered stages, the copper sheet providing increased thermal conductivity while the epoxy electrically isolates the one stage from the other. However, the method disclosed therein of tiering stages of PN thermal elements is labor intensive and, in addition, it is of critical importance that the epoxy in its uncured state and the thickness thereof be carefully controlled to provide a strong bond. Also, the clearances between the stages and the copper plate must be carefully controlled to prevent electrical short circuits with the thermoelectric stages. It is also apparent that by connecting the stages together with external wires, the process is labor intensive and not readily amenable to machine assembly.
A need has thus arisen for a method and apparatus for improving the thermal performance between connected tiers of thermoelectric stages (over that anticipated by a device described in U.S. Pat. No. 4,493,939), as well as methods of fabrication applicable to mass production techniques.